4 5 6 7 8 9 10 19 20 21 22 23 24 25 load supply bb v out 2 out 7 out 8 dwg. pp-029-7 out 19 out 18 out 13 12 13 14 27 28 17 18 serial data out blanking logic supply strobe ground clock clk st blnk out 9 out 10 out 12 out 11 11 latches register register latches 2 326 27 28 serial data in out 6 out 1 out 4 out 3 out 20 1 15 16 out 5 out 17 out 16 out 15 out 14 dd v dabic-iv, 20-bit serial-input, latched source driver a6812xa (dip) data sheet 26182.126b* absolute maximum ratings at t a = 25 c logic supply voltage, v dd ................... 7.0 v driver supply voltage, v bb ................... 60 v continuous output current range, i out ......................... -40 ma to +15 ma input voltage range, v in ....................... -0.3 v to v dd + 0.3 v package power dissipation, p d ........................................ see graph operating temperature range, t a (suffix ?) .................. -40 c to +85 c (suffix ?) ................ -40 c to +125 c (suffix ?) .................. -20 c to +85 c storage temperature range, t s ............................... -55 c to +125 c caution: these cmos devices have input static protection (class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. the a6812C devices combine a 20-bit cmos shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. designed primarily to drive vacuum-fluorescent displays, the 60 v and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. the a6812C features an increased data input rate (com- pared with the older ucn/ucq5812-f) and a controlled output slew rate. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 3.3 v or 5 v logic supply, they will operate to at least 10 mhz. a cmos serial data output permits cascade connections in applica- tions requiring additional drive lines. similar devices are available as the a6810C (10 bits) and a6818C (32 bits). the a6812C output source drivers are npn darlingtons, capable of sourcing up to 40 ma. the controlled output slew rate reduces electro- magnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. for inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a blank- ing input high. the pnp active pull-downs will sink at least 2.5 ma. three temperature ranges are available for optimum performance in commercial (suffix s-), industrial (suffix e-), or automotive (suffix k-) applications. package styles are provided for through-hole dip (suffix -a), surface-mount soic (suffix -lw), or minimum-area surface-mount plcc (suffix -ep). copper lead frames, low logic- power dissipation, and low output-saturation voltages allow these drivers to source 25 ma from all outputs continuously to more than +43 c (suffix -lw), +61 c (suffix -ep), or +77 c (suffix -a). features controlled output slew rate high-speed data storage 60 v minimum output breakdown high data input rate pnp active pull-downs low output-saturation voltages complete part number includes a suffix to identify operating temperature range (e-, k-, or s-) and package type (-a, -ep, or -lw). always order by complete part number, e.g., a6812slw . 6812 low-power cmos logic and latches improved replacements for tl5812? ucn5812? and ucq5812
6812 20-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 a6812xlw (soic) 4 5 6 7 8 9 10 19 20 21 22 23 24 25 load supply bb v out 2 out 7 out 8 dwg. pp-029-8 out 19 out 18 out 13 12 13 14 27 28 17 18 serial data out blanking logic supply strobe ground clock clk st blnk out 9 out 10 out 12 out 11 11 latches register register latches 2 326 27 28 serial data in out 6 out 1 out 4 out 3 out 20 1 15 16 out 5 out 17 out 16 out 15 out 14 dd v typical input circuit dwg. ep-010-5 in v dd 2 3 4 5 6 7 8 9 12 13 14 15 16 28 1 v dd dwg. pp-059-1 out 10 out 20 out 11 out 19 register latches v bb clock st clk 26 27 22 23 24 25 serial data out load supply serial data in 10 11 strobe ground logic supply 19 20 21 blanking 17 18 out 9 out 1 out 2 out 8 out 18 out 12 latches register 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in c 2.0 1.5 1.0 25 dwg. gp-024-2 suffix 'lw', r = 66 c/w ja suffix 'ep', r = 55 c/w ja suffix 'a', r = 45 c/w ja v bb dwg. ep-021-19 out n typical output driver copyright ?2000, 2003 allegro microsystems, inc. a6812xep (plcc)
6812 20-bit serial-input, latched source driver www.allegromicro.com functional block diagram truth table serial shift register contents serial latch contents output contents data clock data strobe input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n blanklng i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n lp 1 p 2 p 3 ... p n-1 p n x x x ... x x h l l l ... l l l = low logic level h = high logic level x = irrelevant p = present state r = previous state mos bipolar out 1 out 2 ground dwg. fp-013-1 out 3 out n clock serial data in strobe blanking serial data out serial-parallel shift register latches v dd v bb logic supply load supply
6812 20-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 electrical characteristics at t a = +25 c (a6812s-) or over operating temperature range (a6812e- or a6812k-), v bb = 60 v unless otherwise noted. limits @ v dd = 3.3 v limits @ v dd = 5 v characteristic symbol test conditions mln. typ. max. min. typ. max. units output leakage current i cex v out = 0 v <-0.1 -15 <-0.1 -15 a output voltage v out(1) i out = -25 ma 57.5 58.3 57.5 58.3 v v out(0) i out = 1 ma 1.0 1.5 1.0 1.5 v output pull-down current i out(0) v out = 5 v to v bb 2.5 5.0 2.5 5.0 ma input voltage v in(1) 2.2 3.3 v v in(0) 1.1 1.7 v input current i in(1) v in = v dd <0.01 1.0 <0.01 1.0 a i in(0) v in = 0 v <-0.01 -1.0 <-0.01 -1.0 a input clamp voltage v ik i in = -200 a -0.8 -1.5 -0.8 -1.5 v serial data output voltage v out(1) i out = -200 a 2.8 3.05 4.5 4.75 v v out(0) i out = 200 a 0.15 0.3 0.15 0.3 v maximum clock frequency f c 10* 10* mhz logic supply current i dd(1) all outputs high 0.25 0.75 0.3 1.0 ma i dd(0) all outputs low 0.25 0.75 0.3 1.0 ma load supply current i bb(1) all outputs high, no load 3.0 6.0 3.0 6.0 ma i bb(0) all outputs low 0.2 20 0.2 20 a blanking -to- output delay t dis(bq) c l = 30 pf, 50% to 50% 0.7 2.0 0.7 2.0 s t en(bq) c l = 30 pf, 50% to 50% 1.8 3.0 1.8 3.0 s strobe -to- output delay t p(sth-ql) r l = 2.3 k ? , c l 30 pf 0.7 2.0 0.7 2.0 s t p(sth-qh) r l = 2.3 k ? , c l 30 pf 1.8 3.0 1.8 3.0 s output fall time t f r l = 2.3 k ? , c l 30 pf 2.4 12 2.4 12 s output rise time t r r l = 2.3 k ? , c l 30 pf 2.4 12 2.4 12 s output slew rate dv/dt r l = 2.3 k ? , c l 30 pf 4.0 20 4.0 20 v/ s clock -to- serial data out delay t p(ch-sqx) i out = 200 a 50 50 ns negative current is defined as coming out of (sourcing) the specified device terminal. typical data is is for design information only and is at t a = +25 c. * operation at a clock frequency greater than the specified minimum is possible but not warranteed.
6812 20-bit serial-input, latched source driver www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the blanking input be high during serial data entry. when the blanking input is high, the output source drivers are disabled (off); the pnp active pull-down sink drivers are on. the information stored in the latches is not affected by the blanking input. with the blanking input low, the outputs are controlled by the state of their respective latches. clock serial data in strobe blanking out n dwg. wp-029 50% serial data out data data 10% 90% 50% 50% 50% c a b d e low = all outputs enabled p(sth-ql) t p(ch-sqx) t data p(sth-qh) t blanking out n dwg. wp-030a data 10% 50% en(bq) t dis(bq) t high = all outputs blanked (disabled) r t f t 50% 90% a. data active time before clock pulse (data set-up time), t su(d) ...................................... 25 ns b. data active time after clock pulse (data hold time), t h(d) ............................................ 25 ns c. clock pulse width, t w(ch) ............................................ 50 ns d. time between clock activation and strobe, t su(c) .... 100 ns e. strobe pulse width, t w(sth) .......................................... 50 ns note ?timing is representative of a 10 mhz clock. higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.
6812 20-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 A6812EA, a6812ka, & a6812sa dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 12 devices. 28 1 2 3 0.250 max 0.070 0.030 0.015 min 0.022 0.014 0.015 0.008 0.600 bsc dwg. ma-003-28 in 14 0.100 bsc 0.005 min 0.200 0.115 4 0.700 max 15 1.565 1.380 0.580 0.485 28 14.73 12.32 1 2 3 6.35 max 1.77 0.77 0.39 min 0.558 0.356 0.381 0.204 15.24 bsc dwg. ma-003-28 mm 14 2.54 bsc 0.13 min 5.08 2.93 4 17.78 max 15 39.7 35.1
6812 20-bit serial-input, latched source driver www.allegromicro.com a6812eep, a6812kep, & a6812sep (add tr to part number for tape and reel) dimensions in inches (controlling dimensions) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 38 devices or add ?r?to part number for tape and reel. 18 12 0.020 min 0.050 bsc 1 28 index area dwg. ma-005-28a in 0.026 0.032 0.013 0.021 26 25 19 11 4 5 0.165 0.180 0.495 0.485 0.456 0.450 0.495 0.485 0.456 0.450 0.219 0.191 0.219 0.191 0.51 min 4.57 4.20 1.27 bsc 12.57 12.32 11.582 11.430 1 28 index area dwg. ma-005-28a mm 0.812 0.661 0.331 0.533 12.57 12.32 26 25 19 18 12 11 4 5 11.58 11.43 5.56 4.85 5.56 4.85 dimensions in millimeters (for reference only))
6812 20-bit serial-input, latched source driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 a6812elw, a6812klw, & a6812slw (add tr to part number for tape and reel) dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 27 devices or add ?r?to part number for tape and reel. 0 to 8 1 28 2 3 18.10 17.70 0.51 0.33 2.65 2.35 0.10 min. 0.32 0.23 1.27 0.40 dwg. ma-008-28a mm 1.27 bsc 15 7.60 7.40 10.65 10.00 0 to 8 1 2 3 0.020 0.013 0.0040 min. dwg. ma-008-28a in 0.050 bsc 28 15 0.0125 0.0091 0.050 0.016 0.2992 0.2914 0.419 0.394 0.7125 0.6969 0.0926 0.1043
6812 20-bit serial-input, latched source driver www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
|
